Pipelined Processor in Verilog
Writing a full processor in Verilog was one of the most rewarding projects I was ever involved with at Iowa State. The project was a perfect culmination to several classes in a row, requiring knowledge of assembly, basic logic design, processor theory, and a good deal of creative thinking.
I learned a huge amount about processor design and especially instruction encoding through the process. It was also the first large project I had accomplished with a partner. The project was too large for one person to do effectively, but adding more people would have hindered progress.
CPU Final Report
Example Code for the CPU
Datapath diagram (click for full size image)
Results for multiply code (click for full size image)
Results for Fibonacci code (click for full size image)